1. Field of the Invention
The present invention relates to a static electricity chuck which is used to adsorptively hold a wafer in a manufacturing apparatus for a semiconductor device such as an etching device or the like, and a wafer stage having the static electricity chuck.
2. Description of Related Art
Recently, a technical requirement for the micromachining in a super LSI technique has been increasingly severer. For example, with respect to an etching treatment, it is indispensable to use a treatment method which can achieve both a high-precision micromachining which suppress a dimensional conversion difference as much as possible, and a high selection ratio to a back layer.
It is well known that when materials other than oxide film are subjected to a plasma etching treatment, a so-called side wall protection film is used to ensure an anisotropic shape. That is, when reaction products generated during the plasma etching treatment are re-dissociated in plasma, and these re-dissociated materials are deposited as various kinds of deposits such as organic polymer, etc. on the side walls of a pattern to thereby form a side wall protection film. The side wall protection film thus formed serves to protect the side walls from being etched.
As described above, the side wall protection film is formed by the deposits which are generated from the reaction products. Therefore, when a pattern formed by an etching treatment is convex, the thickness of the side wall protection wall is relatively larger as the width of the pattern is finer, and thus the whole pattern width is liable to be still smaller than a desired width. Accordingly, as described above, the fineness of each pattern is promoted, and if the pattern width is small (narrow), the dimensional precision of the pattern thus obtained is reduced when the anisotropy of the etching is achieved by using the side wall protection film.
In order to solve the above disadvantage, a technique of performing an etching treatment while exhausting at high speed has been recently attempted and considered to ensure the dimensional precision. In this high-speed exhausting process, a pump having a higher exhausting speed than a conventional etching treatment apparatus is secured, and the conductance of etching gas is improved to shorten the residence time of the etching gas during the etching treatment, whereby the re-dissociation of reaction products in plasma is suppressed during the etching treatment. According to the high-speed exhausting process as described above, the amount of deposits which are generated by the re-dissociation of the reaction products can be greatly reduced, so that the absolute value of the dimensional conversion difference and the dispersion thereof can be remarkably suppressed.
However, in the high-speed exhausting process as described above, the reaction products are quickly exhausted, resulting in reduction of a supply source for forming a side wall protection film. Therefore, a side wall protection film is not formed at a sufficient thickness, and the anisotropic shape is not sufficiently ensured. Accordingly, there occurs a new problem that the precision in shape of a pattern obtained when an overetching is carried out is lowered.
That is, when a substrate-applied bias is lowered to ensure the selection ratio to the back layer in the overetching process, occurrence of side etching or notching is unavoidable because the side wall protection film is thin and thus weak. On the other hand, when the applying bias is increased to ensure the shape precision, the selection ratio to the back layer is lowered.
In view of the foregoing, a low-temperature etching technique for cooling a wafer so that the temperature of the water is reduced to zero degree or less in the etching treatment is proposed as a technique which can solve the trade-off problem between the selection ratio and the shape precision as described above and achieve both the selection ratio and the anisotropic shape. This low-temperature etching technique is proposed by K. Tsujimoto, et al. in "Proceedings of Symposium on Dry Process" pp 42-49 on 24th and 25th of Oct. 1988 in Tokyo.
According to this technique, radical reaction is suppressed by reducing the temperature of samples to keep the anisotropy even under a low substrate-applied bias.
However, this low-temperature etching technique has the following disadvantages.
First, it is difficult to process those materials like W polyside for which reaction products have different vaporization pressures. If the temperature of samples are reduced to a low temperature suitable for etching of polysilicon to etch W polyside because reaction products such as WCl.sub.x, WO.sub.x Cl.sub.y, etc. which are generated by the etching treatment of WSi.sub.x have low vaporization pressure, it would be impossible to perform the etching of WSi.sub.x.
Secondly, .DELTA.T (the difference between a set temperature of a sample stand and wafer temperature) increases during the etching treatment That is, for example, in a contact hole processing work, the setting of the low temperature is effective to ensure the selection ratio to the back layer of Si, however, the low-temperature setting induces the contact hole to be tapered in shape due to excessive deposition of polymer. Therefore, as described above, it is difficult to set the low-temperature condition, and incident energy must be increased to dissociate Si--O bonds in the contact hole processing work, resulting in increase of .DELTA.T.
Accordingly, in the low-temperature etching treatment as described above, the etching must be performed at an incompletely low temperature.
In order to solve this disadvantage, it may be considered that the set temperature of a sample such as wafer or the like is varied between materials whose reaction products are different in vaporization pressure, or between an just etching treatment and an over etching treatment. However, if the set temperature is varied in the midst of the etching treatment, the throughput would be reduced, and it is inconvenient on cost.
Accordingly, there has been required a mechanism which can vary the temperature of a wafer in short time with no effect on the throughput, that is, which enables quick temperature reduction and increase.